1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a system for handling data in a semiconductor memory apparatus.
2. Related Art
A phase change random access memory (PCRAM) is a non-volatile memory apparatus which programs a memory cell through a programming current.
A PCRAM has characteristics of a random access non-volatile memory. Also, the PCRAM can be highly integrated at a low cost. The PCRAM stores data by using a phase change material. Specifically, the PCRAM stores data by using properties for different phases of a phase change material. The phase change material may be at different phases depending on the temperature of the phase change material.
The phase change material can change to either an amorphous state or a crystalline state at different temperature of the phase change material. A representative phase change material is a chalcogenide alloy, such as, for example, Ge2Sb2Te5 composed of germanium (Ge), antimony (Sb), and tellurium (Te). Hence, a phase change material is generally called a “GST.”
When GST is in a crystalline phase and it is heated to a melting point, its crystallinity is lost. Once cooled, it is frozen into an amorphous glass-like state and its electrical resistance is high. By heating the GST to a temperature above its crystallization point, but below the melting point, the GST will transform into a crystalline state with a much lower resistance. The low resistance crystalline state is referred to as a set state and the high resistance amorphous state is referred to as a reset state.
The PCRAM stores data in memory cells, where each memory cell comprises a circuit element made of GST. The GST is changed to the desired phase by sending an appropriate programming current through the GST to apply Joule heating sufficient to reach temperatures needed to change the phase of the GST. Reading the stored data is accomplished by sending a current through the selected phase change material, where the current is not enough to change the phase of the GST.
Since a memory cell has different resistance depending on the phase it is in, a given current will result in different voltage levels for different phase of the GST in that cell. The sensed voltage is interpreted to be a logic value. Generally, a set state is defined as a logic level ‘0’, and a reset state is defined as a logic level ‘1’. However, the specific logic level assigned to a sensed voltage is design dependent. Since the GST changes phases at high temperatures, turning off power to the PCRAM does not affect the phases, and hence the data is non-volatile.
FIG. 1 illustrates a memory cell of a conventional semiconductor memory apparatus including a phase change memory cell.
Referring to FIG. 1, the semiconductor memory apparatus includes a memory unit 110, a programming current driving unit 120, a data reading unit 130, and a global switching unit 140. The memory unit 110 includes a plurality of memory cells MEM_CELL and a plurality of data transfer sections MN10, MN20, and MN30. The plurality of memory cells MEM_CELL are coupled to bit lines BL1, BL2, and BL3 allocated thereto. For reference, the memory cells MEM_CELL comprise a resistive element R1 and a diode D1. The resistive element R1 may be made of a phase change material such as, for example, GST. The plurality of data transfer sections MN10, MN20, and MN30 are coupled between the bit lines BL1, BL2, and BL3 and a global bit line GBL and are selectively turned on in response to selection signals SEL1, SEL2, and SEL3, respectively. Accordingly, data transfer paths are formed between the global bit line GBL and the corresponding bit lines by the turned-on data transfer sections MN10, MN20, and MN30.
When a write enable signal EN_WRITE is activated in a data write mode, the programming current driving unit 120 drives a programming current I_PGM to the global switching unit 140, where the amount of current may depend on which of the write control signals SET_P and RESET_P is asserted. Since the global switching unit 140 is turned on in the data write mode, the programming current I_PGM is supplied to the corresponding memory cell through the global bit line GBL and the specific bit line.
The data reading unit 130 includes a sensing current driving section 131 and a data detection section 132. In the data read mode, the sensing current driving section 131 drives a sensing current I_SENSE to an output node N3. The sensing current I_SENSE flows through the global switching unit 140 to the corresponding memory cell MEM_CELL through the global bit line GBL. The current I_SENSE will induce a voltage across the resistive device R1 of the memory cell MEM_CELL. The voltage level of the output node N3 varies according to the resistance value of the resistive device R1. The data detection section 132 detects the voltage level of the output node N3, compares it to a reference voltage VREF, and outputs read data DATA_READ according.
However, when an excessive sensing current I_SENSE is supplied to the memory cell MEM_CELL, the phase of the resistive device R1 may be changed inadvertently. For example, when the phase change memory cell is supplied with an excessive sensing current I_SENSE in a reset state, it may change to a set state. In order to prevent such a problem, the sensing current driving section 131 includes a clamping transistor MN4. The clamping transistor MN4 adjusts a voltage formed at the memory cell MEM_CELL by limiting the sensing current I_SENSE according to the control of a clamping control signal VCLAMP.
As described above, the conventional semiconductor memory apparatus includes a plurality of current drivers, such as the programming current driving units 120 and the sensing current driving sections 131, which use different operating voltage sources. Therefore, the conventional semiconductor memory apparatus occupies a large circuit area.